The good Lee Ritchey is spitting out a series of very useful posts on the SI-LIST (highly recommended mailing list if you are into signal integrity). Here is another one to clear up the confusion about copper thieving. To preserve it in this context, here is the important stuff:
Thieving is copper added to outer layers of a PCB to create a uniform distribution of copper across the surface. The reason this is done is to make sure the copper plating in the holes is uniform. If the copper distribution in the artwork is not uniform, areas with little exposed copper will plate very heavy while areas with large amounts of copper, such as BGAs or connector pin fields will not plate properly. So, “thieving” steals some of the plating current that would otherwise concentrate on features that are sparse and be spread thin in areas with areas that are dense with features.
Thieving is an outer layer only process. All of the discussions that mention doing things to inner layers are not thieving. They are signal layer fills to even out the resin flow from the prepreg. I have designed thousands of complex PCBs with many signal layers in each one and have never encountered a stackup that required inner layer signal layer fill to achieve a usable, flat PCB.
When a fabricator is allowed to add thieving to outer layers, one only need to keep it away from other features on that layer to comply with typical spacing standards and away from traces enough that it does not adversely affect impedance. If the next layer down is a plane layer, that is all that is needed. If the next layer down is a signal layer (buried microstrip) thieving should not be placed over traces in the buried layer.
If you noticed it, the other common misconception that Lee clears up here is on “copper balancing” to avoid warped boards. There is no need to balance copper on a PCB today. Period.
I noticed someone having trouble understanding this and a friendly profile “Anne C” added this, which I find is a good supplementary explanation:
The manufacturing process for PCBs will require a given type of plating. This is done by a a chemical process involving electric current to plate the bare copper traces. To help have a uniform current from your copper masses (trace, donuts, pads) to the plating solutions, it is better to have a uniform copper coverage, throughout your PCB. If this is not done, current will flow more in areas of your PCB that is busy with copper and less where it is not, throwing out of balance the migration of plating chemical to those copper features. The main problem it creates is a target quality of the plating on vias. When a PCB goes through the multistage oven to reflow the solder paste, bad quality vias may pop and fail. This failure mode occurs at the end of the assembly process and costs a lot in rework costs.
Thanks “Anne C” – whoever you are 🙂
If you want to learn more about board fabrication, this is an essential part of the signal integrity courses we organize for the European engineers under the name of Stockholm SI Week 2015 May 18-22, 2015 in Stockholm. See you there.