My guess is: There is DDR memory as part of that system. And the functionality behind the memory is often not completely understood. The layout is done following the design guide. The memory access settings are taken from the CPU vendors default values.
Without some background know-how it is difficult to judge the impact of even small deviations from the design guide.
This makes troubleshooting quite difficult. The memory interface is getting more and more a „Black Box“! With every new memory generation the margins are getting smaller and the requirements for the design are increasing.
If this sounds like what you experience, you need the know-how for designing successful products in the future now. That is exactly what this course can give you.
- Memory inside: What‘s inside the components?
- Basic commands: How to access the DDR memory?
- ECC: How does it work and how to test it?
- Application Test for Memory
- SPD Content
- Routing and Layout: Real world implementation
- DDR2 vs. DDR3 vs. DDR4: The most important differences!
- Signal Integrity: How to simulate signals?
- Power Integrity: Can the components be supplied with current?
- S-Parameter: How to read data in the frequency domain?
- Compliance Test
Course language is English. Hermann will take questions and off-line discussions in German as well.
|Venue:||Business Center Winghouse, Ørestads Boulevard 73, 2300 Copenhagen S, Denmark|
|Date:||May 30+31, 2017|
|Time:||10:00 to 17:00 on the 1st day
8:30 to 15:30 on the 2nd day
- Expert training two days
- Very comprehensive material in PDF format
- Coffee/tea/water + fruit, pastries and a full lunch
- Signed course certificate
- A limit of 20 participants
Hermann Ruckerbauer is a consultant and owner of EyeKnowHow. Before founding EyeKnowHow, Hermann worked with dynamic memory design at Qimonda AG, Infineon Technologies and Siemens/Infineon for many years.